1 /*---------------------------------------------------------------------*
2 FILENAME: SERIAL.H
3
4 Some definitions used by SERIAL.C
5
6 *--------------------------------------------------------------------*/
7
8 #define COM1 1
9 #define COM2 2
10 #define COM1BASE 0x3F8 /* Base port address for COM1 */
11 #define COM2BASE 0x2F8 /* Base port address for COM2 */
12
13 /*
14 The 8250 UART has 10 registers accessible through 7 port addresses.
15 Here are their addresses relative to COM1BASE and COM2BASE. Note
16 that the baud rate registers, (DLL) and (DLH) are active only when
17 the Divisor-Latch Access-Bit (DLAB) is on. The (DLAB) is bit 7 of
18 the (LCR).
19
20 o TXR Output data to the serial port.
21 o RXR Input data from the serial port.
22 o LCR Initialize the serial port.
23 o IER Controls interrupt generation.
24 o IIR Identifies interrupts.
25 o MCR Send contorl signals to the modem.
26 o LSR Monitor the status of the serial port.
27 o MSR Receive status of the modem.
28 o DLL Low byte of baud rate divisor.
29 o DHH High byte of baud rate divisor.
30 */
31 #define TXR 0 /* Transmit register (WRITE) */
32 #define RXR 0 /* Receive register (READ) */
33 #define IER 1 /* Interrupt Enable */
34 #define IIR 2 /* Interrupt ID */
35 #define LCR 3 /* Line control */
36 #define MCR 4 /* Modem control */
37 #define LSR 5 /* Line Status */
38 #define MSR 6 /* Modem Status */
39 #define DLL 0 /* Divisor Latch Low */
40 #define DLH 1 /* Divisor latch High */
41
42
43 /*-------------------------------------------------------------------*
44 Bit values held in the Line Control Register (LCR).
45 bit meaning
46 --- -------
47 0-1 00=5 bits, 01=6 bits, 10=7 bits, 11=8 bits.
48 2 Stop bits.
49 3 0=parity off, 1=parity on.
50 4 0=parity odd, 1=parity even.
51 5 Sticky parity.
52 6 Set break.
53 7 Toggle port addresses.
54 *-------------------------------------------------------------------*/
55 #define NO_PARITY 0x00
56 #define EVEN_PARITY 0x18
57 #define ODD_PARITY 0x08
58
59
60
61 /*-------------------------------------------------------------------*
62 Bit values held in the Line Status Register (LSR).
63 bit meaning
64 --- -------
65 0 Data ready.
66 1 Overrun error - Data register overwritten.
67 2 Parity error - bad transmission.
68 3 Framing error - No stop bit was found.
69 4 Break detect - End to transmission requested.
70 5 Transmitter holding register is empty.
71 6 Transmitter shift register is empty.
72 7 Time out - off line.
73 *-------------------------------------------------------------------*/
74 #define RCVRDY 0x01
75 #define OVRERR 0x02
76 #define PRTYERR 0x04
77 #define FRMERR 0x08
78 #define BRKERR 0x10
79 #define XMTRDY 0x20
80 #define XMTRSR 0x40
81 #define TIMEOUT 0x80
82
83 /*-------------------------------------------------------------------*
84 Bit values held in the Modem Output Control Register (MCR).
85 bit meaning
86 --- -------
87 0 Data Terminal Ready. Computer ready to go.
88 1 Request To Send. Computer wants to send data.
89 2 auxillary output #1.
90 3 auxillary output #2.(Note: This bit must be
91 set to allow the communications card to send
92 interrupts to the system)
93 4 UART ouput looped back as input.
94 5-7 not used.
95 *------------------------------------------------------------------*/
96 #define DTR 0x01
97 #define RTS 0x02
98 #define MC_INT 0x08
99
100 #define FLOW_RR (DTR|RTS|MC_INT)
101 #define FLOW_RNR (DTR|MC_INT)
102
103
104 /*------------------------------------------------------------------*
105 Bit values held in the Modem Input Status Register (MSR).
106 bit meaning
107 --- -------
108 0 delta Clear To Send.
109 1 delta Data Set Ready.
110 2 delta Ring Indicator.
111 3 delta Data Carrier Detect.
112 4 Clear To Send.
113 5 Data Set Ready.
114 6 Ring Indicator.
115 7 Data Carrier Detect.
116 *------------------------------------------------------------------*/
117 #define CTS 0x10
118 #define DSR 0x20
119
120 #define CTS_ASSERTED 0x11
121
122 /*------------------------------------------------------------------*
123 Bit values held in the Interrupt Enable Register (IER).
124 bit meaning
125 --- -------
126 0 Interrupt when data received.
127 1 Interrupt when transmitter holding reg. empty.
128 2 Interrupt when data reception error.
129 3 Interrupt when change in modem status register.
130 4-7 Not used.
131 *------------------------------------------------------------------*/
132 #define RX_INT 0x01
133 #define TX_INT 0x02
134 #define ERROR_INT 0x04
135 #define MSR_INT 0x08
136 #define ALL_INT 0x0F
137
138 /*------------------------------------------------------------------*
139 Bit values held in the Interrupt Identification Register (IIR).
140 bit meaning
141 --- -------
142 0 Interrupt pending
143 1-2 Interrupt ID code
144 00=Change in modem status register,
145 01=Transmitter holding register empty,
146 10=Data received,
147 11=reception error, or break encountered.
148 3-7 Not used.
149 *------------------------------------------------------------------*/
150 #define IIR_MSR 0x00
151 #define IIR_PENDING 0x01
152 #define IIR_TX 0x02
153 #define IIR_RX 0x04
154 #define IIR_ERROR 0x06
155 #define IIR_MASK 0x07
156
157 /*
158 These are the port addresses of the 8259 Programmable Interrupt
159 Controller (PIC).
160 */
161 #define IMR 0x21 /* Interrupt Mask Register port */
162 #define ICR 0x20 /* Interrupt Control Port */
163
164
165 /*
166 An end of interrupt needs to be sent to the Control Port of
167 the 8259 when a hardware interrupt ends.
168 */
169 #define EOI 0x20 /* End Of Interrupt */
170
171
172 /*
173 The (IMR) tells the (PIC) to service an interrupt only if it
174 is not masked (FALSE).
175 */
176 #define IRQ3 0xF7 /* COM2 */
177 #define IRQ4 0xEF /* COM1 */
178
179
180 /*
181 The (IMR) tells the (PIC) to service an interrupt only if it
182 is not masked (FALSE).
183 */
184 #define IRQ3 0xF7 /* COM2 */
185 #define IRQ4 0xEF /* COM1 */
186
187
188
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